1. Field of the Invention
The invention relates to integrated optical circuits generally and, more particularly, to integrated optical circuits having dense and substantially planar cladding layers formed over optical core waveguiding elements and methods of making such optical circuits. The combination of optical core and cladding layer creates an optical waveguide that may be combined with other optical waveguides and/or devices (such as ring resonators, arrayed waveguide grating multiplexers/demultiplexers, optical add/drop multiplexers, optical switches, variable attenuators, polarization splitters/combiners, multimode interference (MMI) couplers, Mach-Zehnder interferometers, tunable filters, and dispersion compensators) on a substrate to form an integrated optical device or planar lightwave circuit useful for optical communications.
2. Description of the Related Art
Planar optical waveguides are the key building block for integrated optical circuits. A typical planar optical waveguide is formed on a substrate covered with a buffer/cladding layer, a core layer in which waveguiding elements are defined, and a cladding layer surrounding the waveguiding elements. Conventional methods of forming optical waveguides on a substrate to make an optical device, integrated optical device, or planar lightwave circuit typically rely on one of two general methods to deposit the optical cladding layer over an optical core: flame hydrolysis or vapor deposition. One known conventional cladding deposition method uses a single step vapor process such as plasma-enhanced chemical vapor deposition (PECVD). Prior art single-step vapor deposition methods tend to produce poor results for the optical cladding layer due to the interaction of local topography (e.g., the core waveguiding elements positioned on the substrate) and the fundamentally conformal nature of CVD growth shadowing and coating overhangs resulting from the large variations in local topography.
FIG. 1 schematically depicts a representative planar waveguide for an optical integrated circuit formed via conventional, single-step vapor deposition. Waveguide 10 includes a substrate 20, buffer layer 30, waveguiding core elements 40, and cladding layer 50. Various defects exist in the cladding layer as a result of the prior art process. Element 52 depicts the substantially non-planar topography formed in which the final upper cladding surface exhibits local non-planar features with a height deviation approximating that of the original waveguide core height. Large topographic features on the cladding layer require application of a planarization process to achieve a sufficiently flat final surface. Non-planar surface topography can interfere and distort the optical mode shape in optical waveguide elements 40 as well as make it impossible to form or stack additional optical device features (e.g., additional waveguides, resistive heater elements, sensors) on the surface of cladding 52 without intermediate planarization processes.
For closely-spaced waveguide elements 40, void 54 can form during deposition due to the poor gap filling capability of prior art CVD techniques. In general, gap fill becomes increasingly difficult as the ratio of feature height to feature spacing becomes greater than one. The presence of a void in the optical cladding layer creates a non-uniformity in the optical cladding refractive index that may distort the optical mode shape or cause optical scattering.
A phenomenon having a similar effect as a void is shown as feature 56. Here, two seams (or linear voids) form where the sidewall growth front and the floor growth front meet during the cladding layer deposition step. In addition to physical defects 52, 54, and 56, single step vapor deposition techniques typically create significant stress 58 (and stress-related optical birefringence), in the cladding layer, particularly when a high temperature annealing process is used. Generally, the stress and birefringence vary with position as a function of distance from a starting feature such as the lower clad/buffer layer or optical waveguide core elements. The result is pattern dependent optical birefringence that can greatly affect the polarization performance of optical waveguides and devices such that two orthogonal polarizations behave differently on passing through the device.
Voids and seams in the optical cladding of a waveguide or device create unacceptable non-uniformities in the cladding refractive index that cause optical loss via scattering, optical birefringence in the refractive index, or distortion of the optical mode shape from the optimal design geometry. Even small localized variations in the cladding refractive index (xcex94nxcx9c10xe2x88x924 to 10xe2x88x923) greatly affect the proper operation of a sensitive optical device such as a mode transformer, ring resonator, or interferometer that relies on precise refractive index values and refractive index contrast between clad and core for proper operation.
To avoid some of the cladding problems caused by conventional single-step vapor deposition, U.S. Pat. No. 6,044,292 uses several cycles of alternating vapor deposition and annealing steps. The first step is a low pressure CVD (LPCVD) deposition of a thin borophosphosilicate glass (BPSG) layer followed by a second step comprising high temperature annealing (T greater than 700C) to reflow the BPSG glass. In this manner, a 20 xcexcm optical cladding layer can be slowly built after several alternating sequences of deposition and annealing. Although this technique tends to eliminate formation of voids 42, there are several drawbacks. First, the extended process time associated with a multi-step process as well as high temperature annealing increases cost and decreases yield. Second, the resulting cladding layer typically has nonplanar topography as seen in the figure of the ""044 patent. Further, the cladding layer may experience annealing-related stress due to mismatch among the coefficients of thermal expansion (CTE) of the various layer and substrate materials. This stress creates optical birefringence in the cladding layer refractive index. Often, this birefringence varies depending on the distance from a feature or features on the wafer (pattern dependent birefringence) as the dynamics of the glass reflow process can be influenced by the presence of rigid non-flowing structures nearby (e.g., the waveguiding core elements). The use of BPSG limits the refractive index choice for the cladding layer to a narrow region near 1.46. Additionally, high temperature annealing severely limits substrate choices both in terms of the material selected (which must be able to withstand such temperatures) and in terms of any devices previously formed on the selected substrate that may be destroyed during annealing.
Two other potential methods for depositing an optical cladding layer to form a waveguide are physical vapor deposition such as sputter deposition (DC sputter deposition, reactive sputter deposition, RF sputter deposition, or magnetron sputter deposition), and polymer coating of optical materials. These two methods are currently less common in optical waveguide applications than the previously mentioned vapor deposition methods. Sputter coatings tend to suffer from similar problems as vapor deposition in that the finished cladding layer is non-planar, the gap fill capability is poor, and voids may be present in the cladding. These coatings are difficult to deposit with precise index control and good uniformity. Polymer cladding layers avoid most of these problems and often produce planar and void-free optical cladding layers. However, polymer materials are not as robust, their refractive index is not as temporally, thermally and environmentally stable as silica-containing glasses, and they tend to have moderate to high values of optical birefringence.
Therefore, there is a need in the art for improved cladding layers for planar waveguides forming optical integrated circuits. The cladding layers must be dense (no voids), exhibit a substantially uniform refractive index throughout the cladding, and have sufficiently planar cladding surfaces.
The present invention overcomes the disadvantages of prior integrated optical circuits by providing an integrated optical circuit having a dense, void-free, and uniform stress cladding layer that is sufficiently planar such that further layers may optionally be provided on the cladding layer without an intermediate planarization step.
The integrated optical circuit includes a substrate with a first cladding layer having a first refractive index positioned on the substrate. A first core layer having a core refractive index is formed on the first cladding layer; the core layer includes one or more defined waveguiding elements. In particular, the present invention permits waveguides to be patterned having a ratio of waveguide height to waveguide spacing of greater than 1 without defects such as voids being formed between the waveguides during subsequent cladding deposition. A second cladding layer having a second cladding refractive index surrounds the waveguiding elements of the first core layer. The second cladding refractive index and the first cladding refractive index are selected to be less than the core refractive index. The second cladding layer is created through a process of simultaneous cladding material deposition and removal, the ratio of cladding material deposition to cladding material removal being approximately greater than 1 and less than 20. In this manner, the second cladding layer is substantially void-free and substantially self-planarizing, enabling further layers to be directly positioned on the second cladding layer without necessitating intermediate planarization (e.g., reflow of the cladding layer, etching, and or polishing).